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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC145745
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V.21/V.23 Telemeter Modem
The MC145745 is a selectable modem chip compatible with ITU V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). The built-in differential line driver has the capability of driving 0 dBm into a 600 load with a 5 V single power supply. This device also includes a DTMF generator, DTMF receiver, call-progress tone detector, answer tone generator, and a receive timing control circuit. Besides having a clock generator with a crystal oscillator connected to it, the device has a divider circuit to which input of a double frequency clock is possible from external sources, such as from a microcontroller unit (MCU). The serial control port (SCP) permits the MCU to access internal registers for exercising the built-in features. A low consumption device, the MC145745 integrates various functions in a small package. This modem IC is best suited for telemeter and other applications of this type. * * * * * * * * * Conforms to ITU V.21 and V.23 Recommendations DTMF Generator and Receiver for all 16 Standard Digits Capable of Driving 0 dBm into a 600 Load (VCC = 5 V) Automatic Gain Control (AGC) Amplifier for the DTMF Receiver Call-Progress Tone Detector Four-Wire Serial Data Interface (SCP) Programmable Transmission and Carrier Detection Levels FSK/DTMF Analog Loopback Self-Test Function Crystal Oscillator (3.579545 MHz) and Half Divider Circuit (7.159090 MHz) for External Inputs * Operates in the Voltage Range of 3.3 - 5.5 V * Power Down Mode (ICC < 1 A)
28 1
FW SUFFIX SOIC CASE 751M
ORDERING INFORMATION
MC145745FW SOIC
PIN ASSIGNMENT
GND Vref CDA TLA TEST 1 RxD TxD CD CLKO X1 X2 ECLK PB0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC RxA TxA1 TxA2 TEST 2 SCPEN SCPCLK SCP Rx SCP Tx RESET PB3 PB2 PB1 VCC
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0 7/96
(c) Motorola, Inc. 1996 MOTOROLA
MC145745 1
BLOCK DIAGRAM
RxA
Rx AMP AND AGC CONTROL LOOPBACK PATH SMOOTHING FILTER AND Tx GAIN CONTROL 1/2
4 ANTI-ALIAS AND LOW-PASS FILTER TONE GENERATOR DTMF RECEIVER CPT DETECTOR FSK CARRIER DETECTOR FSK V.21 MODEM FSK V.23 MODEM TIMING CONTROL CIRCUIT
PB0 - PB3
CDA Vref
CD
TxA2 TxA1
- +
TxD
RxD
CLKO
CLOCK GENERATOR
RESET
X1
X2
ECLK
TLA
VCC
GND
SCP Tx
SCP Rx SCPEN
SCPCLK
MC145745 2
MOTOROLA
PIN DESCRIPTIONS
Pin Location 1, 14 2 3 Symbol GND Vref CDA Type -- -- -- Description Ground -- These are the ground pins of the digital and the analog circuits. The 0 V potential of the device is determined by the input voltage at these pins. Reference Analog Ground -- This pin provides the analog ground voltage VCC/2, which is regulated internally. This pin should be decoupled to GND with 0.1 F and 100 F capacitors. Carrier Detect Level Adjustment -- The detection level for FSK/call-progress tone is determined according to the voltage at this pin. When VCC = 5 V and the carrier detection level bit (BR3:b1) of the SCP register is 0, or when VCC = 3.6 V and (BR3:b1) is 1, the CDA voltage is set to 1.25 V by the internal divider. This voltage sets the detection levels at ON to OFF: - 44 dBm (typ) and OFF to ON: - 47 dBm (typ). This high impedance pin should be decoupled to GND with a 0.1 F capacitor. The carrier detection level is proportional to the terminal voltage at this pin. An external voltage may be applied to this pin to adjust the carrier detect threshold. The following equations may be used to find the CDA voltage requirements for a given threshold voltage. VCDA = 256 x Von VCDA = 362 x Voff Transmit Level Adjustment -- This pin is used to adjust the transmit carrier level which is determined by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when this pin is shorted to GND (RTLA = 0). Test Pins 1 and 2 -- These test pins are for manufacturer's use only. These pins should be left open in normal operation. Receive Data Output -- This pin is the receive data output. When the device is in the FSK mode, logic high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic low indicates that the space carrier frequency has been received. Transmit Data Input -- This pin is the transmit data input. When the device is in the FSK mode, logic high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the space frequency. Carrier Detect Output -- This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level to avoid erroneous output of received data caused by line noise. Clock Output -- This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device such as the MC74HC04. Crystal Oscillator Circuit Output -- A 3.579545 MHz 0.1% crystal oscillator is tied to this pin with the other end connected to X2. Crystal Oscillator Circuit Input -- A 3.579545 MHz 0.1% crystal oscillator is tied to this pin with the other end connected to X1. X2 may be driven directly from an appropriate external clock source. External Clock Input -- ECLK is the input of double frequency, 7.159090 MHz 0.1%, of the reference clock. This pin must be connected to GND when not in use. DTMF Receive Data Parallel Output 0 (LSB) -- Pins 13, 16, 17, and 18 are the DTMF receive data parallel output occurring together with the CD (Pin 8) data valid output. The outputs of these pins are valid as long as the CD pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and these pins are in high impedance. Positive Power Supply -- These are the power supply pins for the digital and the analog circuits. These pins should be decoupled to GND with 0.1 F and 100 F capacitors. DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) -- These pins are the DTMF receiver data parallel outputs. See pin 13 for more details details. outputs Reset -- A high to low trigger pulse applied to this pin sets all the registers in the default state. It should remain at high during normal operations. SCP Output Transmit -- Refer to Serial Control Port (SCP Interface) for additional information. SCP Receive Input -- Refer to Serial Control Port (SCP Interface) for additional information. SCP Clock -- Refer to Serial Control Port (SCP Interface) for additional information. SCP Enable -- Refer to Serial Control Port (SCP Interface) for additional information.
4
TLA
--
5, 24 6
TEST 1, TEST 2 RxD
I/O O
7
TxD
I
8
CD
O
9 10 11 12 13
CLKO X1 X2 ECLK PB0
O O I I O
15, 28 16, 17, 18 19 20 21 22 23
VCC PB1, PB2, PB3 RESET SCP Tx SCP Rx SCPCLK SCPEN
-- O I O I I I
MOTOROLA
MC145745 3
PIN DESCRIPTIONS (continued)
Pin Location 25 Symbol TxA2 Type O Description Transmit Buffer Output 2 (Inverting) -- This pin is the inverting output of the line driver. When VCC = 5 V, + 7 dBm (typ), differential output voltage (VTxA1 - VTxA2), can be obtained with a load of 1.2 k between pins TxA1 and TxA2. In typical applications, the output level on the telephone line will be half of the differential output (refer to Application Circuit). Transmit Buffer Output 1 (Non-Inverting) -- This pin is the non-inverting output of the line driver. Refer to TxA2. Receive Signal Input -- This pin is the analog signal input which has 500 k input resistance (typ).
26 27
TxA1 RxA
O I
ABSOLUTE MAXIMUM RATINGS
Rating DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Power Dissipation Storage Temperature Range Symbol VCC Vin Vout Iin Iout PD Tstg Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 500 - 65 to + 150 Unit V V V mA mA mW C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range GND (Vin or Vout) VCC. Reliability of operation is enhanced if unused logic inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
v
v
RECOMMENDED OPERATIONAL CONDITIONS
Parameter DC Supply Voltage DC Input Voltage DC Output Voltage Crystal Oscillation Frequency External Input Frequency (ECLK) Operating Temperature Range TA Symbol VCC Vin Vout fosc Min 3.3 0 0 -- -- - 30 Typ 5.0 -- -- 3.579545 7.15909 25 Max 5.5 VCC VCC -- -- + 85 C Unit V V V MHz
DC ELECTRICAL CHARACTERISTICS (VCC = + 3.3 to + 5.5 V, TA = - 30 to + 85C)
Characteristic Input Voltage (TxD, ECLK, RESET, ( SCP R SCPCLK Rx, SCPCLK, SCPEN) Output Voltage (RxD, CD, CLKO (RxD CD CLKO, PB0-3, SCP Tx) High Level Low Level High Level Low Level Symbol VIH VIL VOH VOL Vin = VIH or VIL, Iout = 20 A Vin = VIH or VIL Iout = 20 A Iout = 2 mA Vin = VCC or GND Conditions Min 0.7 x VCC -- VCC - 0.1 -- -- -- Typ -- -- VCC - 0.01 0.01 -- 1.0 Max -- 1.1 -- 0.1 0.4 10.0 A Unit V
Input Leakage Current (TxD, ECLK, RESET, SCP Rx, SCPCLK, SCPEN) Quiescent Supply Current VCC = 5 V
Iin
ICC
FSK Mode, RTLA = 0 TxA1 and TxA2 open DTMF Receive Mode, no input
-- -- -- -- -- --
7 9 6 8 -- --
-- -- -- -- 500 1.0
mA
VCC = 3.6 V
ICC
FSK Mode, RTLA = 0 TxA1 and TxA2 open DTMF Receive Mode, no input
Power-Down Supply Current
ICC
Power-Down Mode 1 Power-Down Mode 2
A A
MC145745 4
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(VCC = + 3.6 V 0.3 V, TA = - 30 to + 85_C) TRANSMIT CARRIER CHARACTERISTICS
Characteristic V.21 Carrier Frequency Originate Mode V.21 Carrier Frequency Answer Mode V.23 Carrier Frequency Mark "1" Space "0" Mark "1" Space "0" Mark "1" Space "0" Transmit Carrier Level Secondary Harmonic Level Out-of-Band Level Symbol f1M f1S f2M f2S f1M f1S VO V2h VOE Transmit Attenuator = 0 dB RTLA = 0 RL = 1 2 k 0, 1.2 VTxA1 - VTxA2 Conditions Oscillation Frequency: 3.579545 3 579545 MHz (X2) or 7.159090 MHz (ECLK) Min 974 1174 1644 1844 1294 2094 -- -- Typ 980 1180 1650 1850 1300 2100 4 - 40 Refer to Figure 1 Max 986 1186 1656 1856 1306 2106 -- -- dBm dB dBm Unit Hz
TRANSMIT ATTENUATOR CHARACTERISTICS
Characteristic Attenuation Range Attenuator Accuracy 1 - 5 dB 6 - 9 dB 10 - 15 dB Symbol Conditions Min 0 - 0.5 -1 - 1.7 Typ -- -- -- -- Max 15 0.5 1 1 Unit dB dB
RECEIVER CHARACTERISTICS (Includes Hybrid, Demodulator, and Carrier Detector)
Characteristic Input Resistance Receive Carrier Amplitude Carrier Detection Threshold OFF to ON ON to OFF Symbol RIRX VIRX VCDON VCDOFF HYS TCDON CD1 = 0, CD0 = 0, CD Pin CD1 = 0, CD0 = 1, CD Pin CD1 = 1, CD0 = 0, CD Pin CD1 = 1, CD0 = 1, CD Pin ON to OFF TCDOFF CD1 = 0, CD0 = 0, CD Pin CD1 = 0, CD0 = 1, CD Pin CD1 = 1, CD0 = 0, CD Pin CD1 = 1, CD0 = 1, CD Pin CDA = 1.25 V fi = 1.0 kHz in 1 0 BR3 (b1) = 1 Conditions Min 50 - 48 -- -- 2 -- -- -- -- -- -- -- -- Typ 500 -- - 44 - 47 -- 450 15 15 75 30 30 15 10 Max -- - 12 -- -- -- -- -- -- -- -- -- -- -- dB ms Unit k dBm dBm
Hysteresis (VCDON - VCDOFF) Carrier Detection Timing OFF to ON
CPTD CHARACTERISTICS
Characteristic BPF Center Frequency BPF Pass-Band Lower Cut-Off Frequency BPF Pass-Band Upper Cut-Off Frequency CPT Detection Level VTD ON VTD OFF CPT Detection Timing TTD ON TTD OFF Symbol fc fi fh VTDON VTDOFF TTDON TTDOFF - 3 dB - 3 dB CDA = 1.25 V fi = 400 Hz in BR3 (b1) = 1 Conditions Min -- -- -- -- -- -- -- Typ 400 330 470 - 44 - 47 10 25 Max -- -- -- -- -- -- -- ms Unit Hz Hz Hz dBm
MOTOROLA
MC145745 5
DTMF TRANSMIT CHARACTERISTICS
Characteristic Tone Output Level Low Group High Group High Group Pre-Emphasis DTMF Distortion DTMF Frequency Deviation Out-of-Band Level Setup Time Symbol Vfl Vfh PE DIST fV VOE tosc -- Conditions Transmit Attenuator = 0 dB RTLA = 0 fosc = 3.579545 MHz Single Tone Mode RL = 1.2 k 12 VTxA1 - VTxA2 Min -- -- 0 -- -1 Typ 0 1 -- 5 -- Refer to Figure 1 4 -- Max -- -- 3 -- 1 Unit dBm dBm dB % % dB ms
DTMF RECEIVER CHARACTERISTICS
Characteristic Input Resistance Detection Signal Level (Each Tone) Twist (High/Low Group) Frequency Detection Band Width (Figure 3) Frequency Non-Detection Band Width (Figure 3) DTMF Detection Timing (Figure 2) OFF to ON Delay TDVON CD1 = 0 , CD0 = 0 CD1 = 0 , CD0 = 1 CD1 = 1 , CD0 = 0 ON to OFF Delay TDVOFF CD1 = 0 , CD0 = 0 CD1 = 0 , CD0 = 1 CD1 = 1 , CD0 = 0 BR3 = (0, 0, 1, 0) Symbol Conditions Min 50 - 48 - 10 1.5% + 2 Hz - 1.5% - 2Hz -- -- -- -- -- -- -- Typ 500 -- -- -- -- -- 30 35 45 25 35 25 Max -- 0 10 -- -- 3.5% -- -- -- -- -- -- ms Unit k dBm dB
DEMODULATOR CHARACTERISTICS
Characteristic V.21 Bit Bias V.23 Bit Bias V.21 Bit Error Rate Symbol Conditions Receive Level = - 24 dBm S/N = 4 dB Receive Level = - 24 dBm S/N = 14 dB Receive Level = - 24 dBm S/N = 4 dB 511-Bit Pattern Receive Level = - 24 dBm S/N = 14 dB 511-Bit Pattern Min -- -- -- Typ 5 10 0.00001 Max -- -- -- Unit % %
V.23 Bit Error Rate
--
0.00001
--
MC145745 6
MOTOROLA
0 TRANSMIT CARRIER LEVEL (dBr) 0
3.4 k 4 k
16 k
256 k
f (Hz)
- 25
- 15 dB/OCT.
- 55
Figure 1. Out-of-Band Level
Von
Voff
RxA
ton CD
toff
Figure 2. FSK, DTMF, and CPT Carrier Detection Timing
NO-DETECT
DETECT MINIMUM WIDTH
NO-DETECT
- 3.5%
- 1.5% - 2 Hz
fo
+ 1.5% + 2 Hz
Figure 3. DTMF Frequency Detection Bandwidth
MOTOROLA
EEEEEEEE EEEEEEEE
+ 3.5%
EEEEEEEE EEEEEEEE
MC145745 7
SCP TIMING CHARACTERISTICS
Ref. No. 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic SCPEN Active Before Rising Edge of SCPCLK SCPCLK Rising Edge Before SCPEN Active SCP Rx Setup Time Before SCPCLK Rising Edge SCP Rx Hold Time After SCPCLK Rising Edge SCPCLK Period SCPCLK Pulse Width (Low) SCPCLK Pulse Width (High) SCP Tx Active Delay Time SCPCLK Falling Edge to SCP Tx High Impedance SCPEN Inactive Before SCPCLK Rising Edge SCPCLK Rising Edge Before SCPEN Inactive SCPCLK Falling Edge to SCP Tx Valid Data Min 50 50 35 20 250 50 50 0 -- 50 50 0 Max -- -- -- -- -- -- -- 50 30 -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns
10
SCPEN
2
1 5
11
SCPCLK
1
2
3
4 3
4
5
7
6
6
7
8
9
SCP Rx
R/W
A2
A1
A0
D3
D2
D1
D0
8
12 9
SCP Tx
D3
D2
D1
D0
Figure 4. Serial Control Port Timing
MC145745 8
MOTOROLA
DEVICE DESCRIPTION
The MC145745 is a selectable modem chip compatible with V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). This device includes a DTMF generator, DTMF receiver, call-progress tone detector, answer tone generator, and a receive timing control circuit. The built-in differential line driver has the capability of driving 0 dBm into a 600 load with a 5.0 V single power supply. The MC145745 also includes a serial control port (SCP) that permits an MCU to exercise the built- in features. The MC145745 provides an SCP interface to access an internal byte register which controls the device operations; such as function mode, carrier detect timing, transmit/receive gain, and transmit tones. The transmit and receive amplifiers' gain is programmable by SCP register setting (BR4). The TLA pin is also available to adjust the transmit level that is determined by the resistor (RTLA) value connected between the pin and GND. The DTMF receiver amplifier includes a built-in AGC amplifier which automatically adjusts the input amplifier gain corresponding to the amplitude of the DTMF tone input signal. The AGC dynamic range can be selected in four options. The highest received sensitivity obtained is approximately - 50 dBm when the dynamic range of the AGC amplifier is maximized. The tone generator, which can generate 16 DTMF tones, is used at the terminal for transmission of the call and control tones. In addition, a single tone can be generated for tests and other uses. Power down is amenable to software control by setting the byte register BR2. While the device is in the power down state, SCP still operates independently. There are two power down options available: power down 1 (the system clock operates alone) and power down 2 (the system clock stops). The clock generator constitutes an oscillation circuit with a 3.58 MHz crystal connected between the X1 and X2 pins. This device also has a 7.15909 MHz external clock input (ECLK), which has a clock divider circuit for providing a 3.58 MHz clock to the internal circuits. If the ECLK pin is used, the X2 pin should be held low. If the oscillation circuit (X1 and X2) is used, the ECLK pin should be held low. This device also has a clock buffer output (CLKO), which can be used for providing a 3.58 MHz clock to the external device. Table 1 shows the clock input and output relations in the different modes. Table 1. Clock Selection Truth Table
Input Function M d F i Mode ECLK (Pin 12) 0 Power D P Down 1 fext 0 Power D P Down 2 fext 0 Other Mode Oh M d fext X2 (Pin 11) fxtal 0 X 0 fxtal 0 Output CLKO (Pin 9) fxtal fext/2 0 0 fxtal fext/2
SERIAL CONTROL PORT (SCP INTERFACE)
The MC145745 is equipped with an SCP. The SCP is a full-duplex four-wire interface with control and status information passed to and from the internal register. The SCP is compatible with the Serial Peripheral Interface (SPI) of single chip MCUs used in other standard Motorola devices. The SCP consists of SCP Tx, SCP Rx, SCPCLK, and SCPEN for transmitting control data, status data, and DTMF receive data between the MCU and the MC145745. The SCPCLK determines the transmission and reception data rates, and the SCPEN governs when the data transaction is to take place. The operation/configuration of the MC145745 is programmed by setting the state of the internal register bit. The control, status, and data information resides in 4-bit wide registers which are accessed via the 8-bit SCP bus transaction. The first four bits of the 8-bit bus transaction are the read/ write direction and the register address. The next four bits are the data written to or read from the internal registers. The SCP interface is independent of the 3.58 MHz master clock. It runs by using SCPCLK as the synchronizing signal. SCP TRANSACTION The SCP interface includes both read and write capabilities, which together comprise the SCP transaction. These SCP transaction functionalities are described below. SCP Read The SCP read action transaction is shown in Figure 5. During the SCP read action, the SCPEN pin must be in the low position. After SCPEN high goes low, then at the first four SCPCLK rising edges, Read/Write (R/W) bit and three address bits (A0 - A2) are shifted into the intermediate buffer register. If the read action is to be performed, the R/W bit must be at 1. And then, at the following four SCPCLK falling edges, the 4-bit chosen register data is shifted out on SCP Tx. SCPEN must be restored to high after this transaction, before another falling edge of SCPCLK is encountered. While SCP Tx is in output mode, SCP Rx is disregarded. Also, whenever SCP Tx is not transmitting data, a high impedance condition is maintained. SCP Write The SCP write action transaction is shown in Figure 6. During the SCP write action, the SCPEN pin must be in the low position. After SCPEN high goes low, then at the first four SCPCLK rising edges, R/W and three address bits (A0 - A2) are shifted into the intermediate buffer register. If the write action is to be performed, the R/W bit must be at 0. And then, at the following four SCPCLK rising edges, the 4-bit data is shifted in from SCP Rx and written into the chosen register. During the write operation, SCP Tx is in high impedance. If the chosen register and/or the chosen bit are "read only," the write action to it has no effect.
MOTOROLA
MC145745 9
SCPEN SCPCLK
SCP Rx
R/W
A2
A1
A0 D3 D2 D1
SCP Tx
HIGH IMPEDANCE
D0
Figure 5. Serial Control Port Read Operation
SCPEN SCPCLK
SCP Rx SCP Tx
R/W
A2
A1
A0
D3
D2
D1
D0
HIGH IMPEDANCE
Figure 6. Serial Control Port Write Operation
DESCRIPTION OF THE SCP TERMINAL The SCP bus is made up of the following four pins. SCP Tx (Pin 20) The SCP Tx pin outputs the control, status, and data information from the 4-bit wide register. During the read action transaction, a R/W bit and the three address bits are shifted in from SCP Rx at four SCPCLK rising edges, subsequent to SCPEN going low. After this, if a read operation is selected, SCP Tx comes out of the high impedance state at the first falling edge of SCPCLK, and outputs the first bit (MSB) of the chosen register. The remaining three bits of the chosen register are shifted out from SCP Tx at the following three SCPCLK falling edges. After the last bit (LSB) is shifted out, SCPEN must return to high. Then SCP Tx returns to the high impedance condition. SCP Rx (Pin 21) The SCP Rx pin is used to input control and data information into the 4-bit wide register. Data is shifted in from SCP Rx at SCPCLK rising edge, while SCPEN is low. The first bit is the R/W bit (1 = read, 0 = write), and the next three
bits address one of seven byte-registers. The address bits are shifted in MSB first. If the write action is chosen, the 4-bit data is shifted in from SCP Rx at the next four SCPCLK rising edges. If the read action is chosen, 4-bit data in the selected register is shifted out on SCP Tx. SCP Rx is ignored while SCPEN is high. SCPCLK (Pin 22) The SCPCLK pin is an input of standard clock for handshaking between SCP and MCU. After SCPEN comes low and the SCP transaction occurs, data is shifted from SCP Rx into the device at the rising edge of SCPCLK, and is shifted out on SCP Tx at the falling edge of SCPCLK. When SCPEN is high, SCPCLK is ignored (i.e., it may be continuous or it can operate in the burst mode). SCPEN (Pin 23) When the SCPEN pin is held low, the SCP transaction is enabled and control, status, and data information is transferred. If SCPEN is returned to high, the SCP action in progress is aborted, and the SCP Tx pin enters a high impedance condition.
MC145745 10
IIIII IIIII IIIII IIIII
IIIII IIIII IIIII IIIII
DON'T CARE DON'T CARE DON'T CARE DON'T CARE
IIII IIII IIII IIII
IIII IIII IIII IIII
MOTOROLA
SCP REGISTER MAP
The MC145745 register map is shown in Table 2. Seven of the 4-bit wide byte registers (BR) are provided in the register block. According to these published specifications, BR signifies each register and the address of SCP data. R/W is the read/write register, and RO is read only. If there is a high to low pulse on the RESET pin or the power supply turns off, this register returns to the default state. The default condition that occurs after a power reset is as follows.
BR0 BR1 BR2 BR3 BR4 BR5 BR6
V.23 Receive, Transmit Enable DTMF CDON = 30 ms, DTMF CDOFF = 25 ms FSK CDON = 450 ms, FSK CDOFF = 30 ms FSK Mode AGC Range = Maximum, Carrier Detect Level: High Transmission Gain = Maximum DTMF Transmission: 941 Hz + 1633 Hz DTMF Reception: Unknown
Table 2. SCP Register Map
Register BR0 (R/W) 0 1 BR1 (R/W) b3 (Bit 3: MSB) Modem Choice V.23 V.21 FSK CDT2 TCDON b3=0, b2=0 : 450 ms b3=0, b2=1 : 15 ms b3=1, b2=0 : 15 ms b3=1, b2=1 : 75 ms BR2 (R/W) (see Table 3) BR3 (R/W) 0 1 BR4 (R/W) (see Table 4) BR5 (R/W) (see Table 5) BR6 (RO) (see Table 5) Function Mode 4 AGC Range 2 b2 (Bit 2) FSK Channel V.21: Answer V.23: Receive V.21: Originate V.23: Transmit FSK CDT1 TCDOFF b3=0, b2=0 : 30 ms b3=0, b2=1 : 30 ms b3=1, b2=0 : 15 ms b3=1, b2=1 : 10 ms Function Mode 3 AGC Range 1 b1 (Bit1) Transmission Enable Enable Disable DTMF CDT2 TCDON b1=0, b0=0 : 30 ms b1=0, b0=1 : 35 ms b1=1, b0=0 : 45 ms Function Mode 2 Carrier Detect Level 1 High Level (Set when VCC = 5 V) Low Level (Set when VCC = 3.6 V) Transmission Gain 2 Tone Transmission 2 DTMF Reception 2 DTMF CDT1 TCDOFF b1=0, b0=0 : 25 ms b1=0, b0=1 : 35 ms b1=1, b0=0 : 25 ms Function Mode 1 Test Normal Test Mode Transmission Gain 1 Tone Transmission 1 DTMF Reception 1 b0 (Bit 0: LSB)
B3=0, b2=0 : - 5 to + 20 dB B3=0, b2=1 : - 5 to + 15 dB b3=1, b2=0 : - 5 to + 10 dB b3=1, b2=1 : - 5 to + 5 dB Transmission Gain 4 Tone Transmission 4 DTMF Reception 4 Transmission Gain 3 Tone Transmission 3 DTMF Reception 3
NOTES: 1. BR0 (b0) is a non-working bit. 2. DTMF Loopback data is entered into BR5 and output from the parallel port.
MOTOROLA
MC145745 11
Table 3. Function Mode Setup
Register FSK Mode FSK Loopback CPT Detect Mode Answer Tone Transmission Mode DTMF Transmission Mode Single Tone Transmission Mode Power Down 1 Power Down 2 DTMF Reception Mode b3 0 0 0 0 0 0 0 0 1 b2 0 0 0 0 1 1 1 1 0 b1 0 0 1 1 0 0 1 1 0 b0 0 1 0 1 0 1 0 1 0 Comments The device works as one of two FSK modes, V.21/V.23. The FSK modulator is internally connected to the FSK demodulator. The device works as the 400 Hz tone detector. The device works as the 2100 Hz answer tone generator. The device works as the DTMF generator. The receiver is disabled. The device outputs one of the eight tones used for DTMF. Whole circuits except for the SCP and the oscillator circuit are disabled. Whole circuits except for the SCP are disabled. The device works as the DTMF receiver. The received DTMF tone is demodulated to the 4-bit code, then output from the SCP interface and/or the parallel port. The DTMF generator is internally connected to the DTMF receiver, then the DTMF code written in BR5 is loopbacked to the parallel port (PB0 - PB3).
DTMF Loopback
1
0
0
1
Table 4. Transmission Attenuator Range
Transmission Attenuator Range 0 dB - 1 dB - 2 dB - 3 dB - 4 dB - 5 dB - 6 dB - 7 dB - 8 dB - 9 dB - 10 dB - 11 dB - 12 dB - 13 dB - 14 dB - 15 dB b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MC145745 12
MOTOROLA
Table 5. Tone Generator/Receiver Data
Tone Generator Tone Receiver Key K Input D 1 2 3 4 5 6 7 8 9 0 * # A B C Low Group Frequency (Hz) 941 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 High Group Frequency (Hz) 1633 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 Single T Si l Tone (Hz) 941 697 697 697 770 770 770 852 1336 1477 1336 1209 1477 1633 1633 1633 b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BR5/BR6 Setting or Data Output
MOTOROLA
MC145745 13
600 : 600 TxD RxD CD I/O PORT SCPEN SCPCLK SCP Rx SCP Tx 4 PB0 - PB3 TEST1 +5V RESET TEST2 MCU TxA2 RxA CDA TLA 0.1 F TxA1 600
10 TIP
*
RING
CLKO ECLK MC145745
Vref 100 F 0.1 F
X1 3.579545 MHz X2
VCC 100 F GND 0.1 F
+5V
*
LINE PROTECTION CIRCUIT
SYSTEM GROUND
REFERENCE ANALOG GROUND
Figure 7. Application Circuit
MC145745 14
MOTOROLA
PACKAGE DIMENSIONS
FW SUFFIX SOIC CASE 751M-01
VIEW AB
28
A -Y-
15
B -Z-
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.65 (0.026). MILLIMETERS MIN MAX 17.80 18.03 7.40 7.62 --- 2.65 2.25 2.45 0.35 0.51 10.00 10.60 0.40 0.70 1.27 BSC 0.10 0.25 0.635 BSC --- 8_ 0.25 0.75 0.05 0.20 1.40 REF INCHES MIN MAX 0.701 0.710 0.291 0.300 --- 0.104 0.090 0.096 0.014 0.020 0.394 0.414 0.016 0.028 0.050 BSC 0.004 0.010 0.025 BSC --- 8_ 0.010 0.030 0.002 0.008 0.055 REF
1 28X D
14
V X 45_ " 5_
0.25 (0.010) 0.18 (0.007)
M M
TZ T
S
Y
S
0.18 (0.007)
M
TY
S
Z
S
C L 0.10 (0.004) T C -T- W
4X SEATING PLANE
VIEW AB
DIM A B C C1 D E F G J L V W X
C1
J
L
24X
G W REF Z F
MOTOROLA
MC145745 15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC145745 16
*MC145745/D*
MC145745/D MOTOROLA

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